1. Field of the Invention
The present invention relates to structures known as “chucks” for supporting wafers such as semiconductor (e.g., silicon) wafers for processing, which could be, but is not limited to, lithography. It furthermore relates to tools for lapping such chucks to impart a desired flatness and roughness, particularly after the chuck has been in service; that is, it also relates to tools for the repair of chucks.
2. Discussion of Related Art
As Moore's Law pushes semiconductor feature sizes smaller and smaller, the need for highly precise wafer handling components grows. The difficulty in achieving the required precision also grows. For instance, the silicon wafers upon which are to be manufactured the microprocessor chips must be precisely placed in the processing machines. The wafers typically are handled by vacuum handling equipment. The wafers droop, ever-so-slightly under their own weight. When lowered to a wafer chuck, the drooping wafer “wants” to flatten out, but may be hindered from doing so by friction between the wafer and chuck. This is sometimes referred to as a “stickiness” problem. Metal oxides are notable in this regard, and silicon dioxide is no exception. Among the efforts to solve, or at least ameliorate, this problem, have been to minimize the contact area between the wafer and the chuck. This particular engineering solution may take the form of designing a plurality of “plateaus” of uniform height, typically regularly spaced, into the wafer. These plateaus are called “pins” or “mesas”, the pins defining a very flat support surface upon which a semiconductor wafer may be placed. The pins help in reducing the friction so that the wafer can move laterally across the mesas as it flattens out upon settling on the mesas. The pins help to reduce wafer sticking, but further improvements in this regard are needed.
With this in mind, key desired features for wafer handling components are high mechanical stability (high stiffness and low density), high thermal stability (high thermal conductivity and low coefficient of thermal expansion), low metallic contamination, machinability to high tolerance, low wear (to maintain precision), low friction (to prevent wafer sticking), and the ability to be fabricated to sizes of up to 450 mm.
Silicon carbide (SiC) has desirable properties for use as a wafer chuck: low density, low thermal expansion coefficient, and high thermal conductivity, to name three.
Silicon carbide-based bodies can be made to near net shape by reactive infiltration techniques, and such has been done for decades. In general, such a reactive infiltration process entails contacting molten silicon (Si) with a porous mass containing silicon carbide plus carbon in a vacuum or an inert atmosphere environment. A wetting condition is created, with the result that the molten silicon is pulled by capillary action into the mass, where it reacts with the carbon to form additional silicon carbide. This in-situ silicon carbide typically is interconnected. A dense body usually is desired, so the process typically occurs in the presence of excess silicon. The resulting composite body thus contains primarily silicon carbide, but also some unreacted silicon (which also is interconnected), and may be referred to in shorthand notation as Si/SiC. The process used to produce such composite bodies is interchangeably referred to as “reaction forming”, “reaction bonding”, “reactive infiltration” or “self bonding”. In more recent technology, for added flexibility, one or more materials other than SiC can be substituted for some or all of the SiC in the porous mass. For example, replacing some of this SiC with diamond particulate can result in a diamond/SiC composite.
It is critical that wafers lie flat against the support surface(s) of the chuck. Otherwise, the circuit pattern images that are projected onto the wafer may be out-of-focus. Furthermore, wafer lithography may involve multiple exposures, with re-location of the wafer between exposures. Thus, it is critical that there be a way to precisely re-align the wafer on the chuck relative to its first positioning so that the subsequent exposures will take place in the correct position on the wafer.
3. Wafer Contamination and Wafer Landing
Why are wafers not flat to begin with? When wafers are processed and by inherent limitations of the manufacture they are not flat. Often processes performed in the front-end semiconductor line add films to the wafer, which results in more-or-less curved wafers. This curvature can be any direction, upward or downwards. The majority of the departure from flat is in curvature and deformation is as a sphere and or cylindrical shape.
Additionally, wafer chucks are never perfectly flat, and often have a slight curvature in a random, manner and orientations like that of a wafer in upwards (bowl) or downwards (dome) shape.
When wafers are located on the wafer chuck that have picked up a curvature due to normal process, they are required to return to the original clamping location by settling to flat. The wafer is required to relax in a manner that is predominately radial.
4. Flatness
Flatness of a part is commonly achieved by one of several well-established methods well known to those experienced in the optical, machining or precision industry.
In a first such method, annular grinding for flat lapping or continuous grinder (CG) uses a table that is maintained as a reference surface more-or-less by external features such as rings or a predominate part called a ‘bruiser’ or ‘conditioner’. There are geometric constraints such as the annular width and diameter of the lap in relation to the part required to be flat and well controlled and repeatable. A constraint to achieve a flat part using table lapping (CG) is that the lapping table needs to maintained to a level of flatness at or better than the desired outcome. Additionally, the uniformity of the pressure and the relative velocity between the parts need to be maintained and controlled. Finally, material uniformity, localized pressure and lap media non-uniformity will cause local and global flatness deviations.
A second approach is to use an ‘over arm’ or ‘spindle lapping’ in which there are two configurations. First, the part to be lapped is moved across a larger flat polishing surface that is spinning, or secondly, the smaller lap tool is moved across the larger part. In each case the relative geometry of the parts are performed in approximately a random manner so the part sees a flat or uniform profile, thereby resulting in a flat part. The tool trajectory profile, pressure uniformity and media distribution all need to be tightly controlled to minimize variations while this is performed.
Each of the mechanical techniques listed above have no direct control of mid and small frequency errors that deviate from flat. Globally, these techniques provide control over a simple geometric shape like a sphere, but rely on uniformity to achieve smaller spatial periods.
Deterministic correction is a final engineering-intensive method, which uses a measurement of the surface and a small tool to use controlled, localized tool impingement. These tools can be mechanical which work by controlling the tool shape, dwell time, pressure, velocity, media (in the MRF), etc. Alternatively, the process can be more sophisticated using etchants, plasma, ions or other localized phenomenon and controlling dwell, tool size, chemistry current, concentration, etc. The limitations of these techniques is the magnitude of the metrology for feedback to generate the ‘hit map’. The metrology must exceed the level of precision that one intends to implement. Failure to do this will result in the addition of more errors.
Often the highest performing flatness is achieved by the application of one or more mechanical techniques, and is followed by a mid and high frequency correction using more advanced methods called deterministic correction. This forces manufacturers and users to invest in more expensive machinery and sophisticated metrology.
When extending conventional techniques listed above to a surface of a wafer chuck with a plateaued, pixilated, pinned or often called a ‘bed of nails’ contact area, conventional machining as described above runs into significant challenges in achieving and maintaining flatness. The challenge is that the plateaued surface may have non-uniform pin distribution, which will result in localized pressure variation, hence flatness variation. Additionally, the pin structure will greatly interfere with loose abrasive media by disrupting the media (grit) distribution. The control of local areas on conventional laps is very difficult and costly and often relies on reducing the material removal rate so the part traverses over different regions of a lap surface many times, resulting in longer process times.
The geometrical constraint of a plateaued surface further limits the techniques by which deterministic correction can be applied. MRF, plasma and CCOS are incapable of dealing with discrete regions, particularly with sparse non-repeating patterns found in the pin structure of wafer chucks due to their need for a continuous surface.
Wafer chucks and the discrete reticulated surface are specified to perform with very stringent mid and high spatial frequency flatness deviations; thus, conventional technologies are struggling to maintain the required evolutionary improvements. The mid and high frequency demand is set forth by the manufacturer of the lithography equipment, whereby the systems measure and pre determine and correct for spatial frequencies larger than the illumination area, such as in the twin scan system of ASML. Typical illumination regions are a rectangle 28 mm by 8 mm; thus, the spatial frequencies of interest to maintain flatness are those less than 28 mm.